A2.5 Coprocessor support ...................................................................... A2-40

Chapter A3 ARM Architecture Memory Model
A3.1 Address space ............................................................................... A3-42
A3.2 Alignment support .......................................................................... A3-43
A3.3 Endian support ............................................................................... A3-44
A3.4 Synchronization and semaphores .................................................. A3-47
A3.5 Memory types and attributes and the memory order model .......... A3-48
A3.6 Access rights .................................................................................. A3-56
A3.7 Memory access order .................................................................... A3-58
A3.8 Caches and memory hierarchy ...................................................... A3-63
Chapter A4 The ARMv6-M Instruction Set
A4.1 About the instruction set ................................................................ A4-66
A4.2 Unified Assembler Language ......................................................... A4-68
A4.3 Branch instructions ........................................................................ A4-70
A4.4 Data-processing instructions .......................................................... A4-71
A4.5 Status register access instructions ................................................ A4-74
A4.6 Load and store instructions ............................................................ A4-75
A4.7 Load Multiple and Store Multiple instructions ................................ A4-77
A4.8 Miscellaneous instructions ............................................................. A4-78
A4.9 Exception-generating instructions .................................................. A4-79
Chapter A5 The Thumb Instruction Set Encoding
A5.1 Thumb instruction set encoding ..................................................... A5-82
A5.2 16-bit Thumb instruction encoding ................................................. A5-84
A5.3 32-bit Thumb instruction encoding ................................................. A5-91
Chapter A6 Thumb Instruction Details
A6.1 Format of instruction descriptions .................................................. A6-94
A6.2 Standard assembler syntax fields .................................................. A6-98
A6.3 Conditional execution ..................................................................... A6-99
A6.4 Shifts applied to a register ........................................................... A6-101
A6.5 Memory accesses ........................................................................ A6-103
A6.6 Hint Instructions ........................................................................... A6-104
A6.7 Alphabetical list of ARMv6-M Thumb instructions ........................ A6-105
Part B System Level Architecture
Chapter B1 System Level Programmers’ Model
B1.1 Introduction to the system level ................................................... B1-204
B1.2 About the ARMv6-M memory mapped architecture ..................... B1-205
B1.3 Overview of system level terminology and operation ................... B1-206
B1.4 Registers ...................................................................................... B1-211
B1.5 ARMv6-M exception model .......................................................... B1-218
Chapter B2 System Memory Model
B2.1 About the system memory model ................................................. B2-246
B2.2 Declarations and support functions .............................................. B2-247
B2.3 Memory accesses ........................................................................ B2-251
B2.4 Control of the endianness model in ARMv6-M ............................. B2-254
B2.5 Barrier support for system correctness ........................................ B2-255
Chapter B3 System Address Map
B3.1 The system address map ............................................................. B3-258
B3.2 System Control Space (SCS) ....................................................... B3-262
B3.3 The system timer, SysTick ........................................................... B3-275
B3.4 Nested Vectored Interrupt Controller, NVIC ................................. B3-281
B3.5 Protected Memory System Architecture, PMSAv6 ....................... B3-289
Chapter B4 ARMv6-M System Instructions
B4.1 About the ARMv6-M system instructions ..................................... B4-304
B4.2 ARMv6-M system instruction descriptions ................................... B4-305
Part C Debug Architecture
Chapter C1 ARMv6-M Debug
C1.1 Introduction to ARMv6-M debug .................................................. C1-316
C1.2 The Debug Access Port ............................................................... C1-318
C1.3 Overview of the ARMv6-M debug features .................................. C1-320
C1.4 Debug and reset .......................................................................... C1-323
C1.5 Debug event behavior .................................................................. C1-324
C1.6 Debug register support in the SCS .............................................. C1-328
C1.7 The Data Watchpoint and Trace unit ........................................... C1-341
C1.8 Breakpoint Unit ............................................................................ C1-351
Part D Appendices
Appendix A ARMv6-M CoreSight Infrastructure IDs
A.1 CoreSight infrastructure IDs for an ARMv6-M implementation .................
AppxA-360
Appendix B Deprecated and Obsolete Features
B.1 Deprecated features of the ARMv6-M architecture ................ AppxB-364
B.2 Obsolete features of the ARMv6-M architecture .................... AppxB-365
Appendix C ARMv7-M Differences
C.1 ARMv6-M and ARMv7-M compatibility .................................. AppxC-368
C.2 About the ARMv6-M and ARMv7-M architecture profiles ...... AppxC-369
C.3 Instruction support ................................................................. AppxC-370
C.4 Programmers’ model support ................................................. AppxC-371
C.5 Memory model support .......................................................... AppxC-373
C.6 System Control Space register support ................................. AppxC-375
C.7 Debug support ....................................................................... AppxC-377
Appendix D Legacy Instruction Mnemonics
D.1 Thumb instruction mnemonics ............................................... AppxD-380
D.2 Pre-UAL pseudo-instruction NOP .......................................... AppxD-384
Appendix E Pseudocode Definition
E.1 Instruction encoding diagrams and pseudocode ................... AppxE-386
E.2 Limitations of pseudocode ..................................................... AppxE-388
E.3 Data types .............................................................................. AppxE-389
E.4 Expressions ........................................................................... AppxE-393
E.5 Operators and built-in functions ............................................. AppxE-395
E.6 Statements and program structure ........................................ AppxE-401
E.7 Miscellaneous helper procedures and functions .................... AppxE-406
Appendix F Pseudocode Index
F.1 Pseudocode operators and keywords .................................... AppxF-410
F.2 Pseudocode functions and procedures .................................. AppxF-414
Appendix G Register Index
G.1 ARM core registers ............................................................... AppxG-422
G.2 Memory mapped system registers ........................................ AppxG-423
G.3 Memory mapped debug registers ......................................... AppxG-424
Glossary