ARM DS-5 ARM DSTREAM System and Interface Design Reference

Chapter 1 Conventions and feedback

Chapter 2 ARM DSTREAM System Design Guidelines

2.1 Using adaptive clocking to synchronize the JTAG port ........................................... 2-2
2.2 Reset signals ........................................................................................................... 2-5
2.3 ARM reset signals .................................................................................................... 2-6
2.4 DSTREAM reset signals .......................................................................................... 2-7
2.5 Example reset circuits .............................................................................................. 2-8
2.6 ASIC guidelines ....................................................................................................... 2-9
2.7 ICs containing multiple devices ............................................................................. 2-10
2.8 Boundary scan test vectors ................................................................................... 2-11
2.9 PCB guidelines ...................................................................................................... 2-12
2.10 PCB connections ................................................................................................... 2-13
2.11 Target interface logic levels ................................................................................... 2-14

Chapter 3 ARM DSTREAM Target Interface Connections

3.1 Signal descriptions ................................................................................................... 3-2
3.2 JTAG port timing characteristics .............................................................................. 3-3
3.3 Serial Wire Debug .................................................................................................... 3-5
3.4 SWD connections .................................................................................................... 3-6
3.5 SWD timing requirements ........................................................................................ 3-7
3.6 Trace signals ........................................................................................................... 3-8
3.7 Target connectors supported by DSTREAM ......................................................... 3-10
3.8 Mictor 38 ................................................................................................................ 3-11
3.9 ARM JTAG 20 ........................................................................................................ 3-15
3.10 TI JTAG 14 ............................................................................................................ 3-18
3.11 ARM JTAG 14 ........................................................................................................ 3-21
3.12 CoreSight 10 .......................................................................................................... 3-24
3.13 CoreSight 20 .......................................................................................................... 3-26
3.14 MIPI 34 .................................................................................................................. 3-29
3.15 I/O diagrams .......................................................................................................... 3-33
3.16 Voltage domains .................................................................................................... 3-36
3.17 Series termination .................................................................................................. 3-37

Chapter 4 ARM DSTREAM User I/O Connections

4.1 The User I/O connector ........................................................................................... 4-2

Chapter 5 Designing the Target Board for Tracing with ARM DSTREAM

5.1 Overview of high-speed design ............................................................................... 5-2
5.2 PCB track impedance .............................................................................................. 5-3
5.3 Signal requirements ................................................................................................. 5-4
5.4 Probe modeling ........................................................................................................ 5-5