The LPC18xx are ARM Cortex-M3 based microcontrollers for embedded applications.The ARM Cortex-M3 is a next generation core that offers system enhancements such aslow power consumption, enhanced debug features, and a high level of support block

integration.

The LPC18xx operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

 The LPC18xx include up to 200 kB of on-chip SRAM data memory (flashless parts) or up to 136 kB of on-chip SRAM and up to 1 MB of flash (parts with on-chip flash), a quad SPIFlash Interface (SPIFI), a State Configurable Timer (SCT) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and

analog peripherals.

Remark: This user manual describes parts LPC1850/30/20/10 (flashless parts) and provides a preliminary description of the flash-based LPC18xx parts.

Processor core

– ARM Cortex-M3 processor, running at frequencies of up to 180 MHz.

– ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.

– ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

– Non-maskable Interrupt (NMI) input.

– JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.

– ETM and ETB support.

– System tick timer.

On-chip memory (flashless parts LPC1850/30/20/10)

– Up to 200 kB SRAM total for code and data use.

– Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be

powered down individually.

– 64 kB ROM containing boot code and on-chip software drivers.

– 32 bit One-Time Programmable (OTP) memory for general-purpose customer use.

On-chip memory (parts with on-chip flash)

– Up to 1 MB total dual bank flash memory with flash accelerator.

– In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

boot loader software.

– Up to 136 kB SRAM for code and data use.

– Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be

powered down individually.

– 64 kB ROM containing boot code and on-chip software drivers.

– 32 bit One-Time Programmable (OTP) memory for general-purpose customer use.

Clock generation unit

– Crystal oscillator with an operating range of 1 MHz to 25 MHz.

– 12 MHz internal RC oscillator trimmed to 1 % accuracy.

– Ultra-low power RTC crystal oscillator.

– Three PLLs allow CPU operation up to the maximum CPU rate without the need for

a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the

third PLL can be used as audio PLL.

– Clock output.

Serial interfaces:

– Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates up to 40 MB per

second.

– 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high

throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time

stamping (IEEE 1588-2008 v2).

– One High-speed USB 2.0 Host/Device/OTG interface with DMA support and

on-chip PHY.

– One High-speed USB 2.0 Host/Device interface with DMA support, on-chip

full-speed PHY and ULPI interface to external high-speed PHY.

– USB interface electrical test software included in ROM USB stack.

– Four 550 UARTs with DMA support: one UART with full modem interface; one

UART with IrDA interface; three USARTs support synchronous mode and a smart

card interface conforming to ISO7816 specification.

– Two C_CAN 2.0B controllers with one channel each.

– Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA

support.

– One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O

pins conforming to the full I2C-bus specification. Supports data rates of up to

1 Mbit/s.

– One standard I2C-bus interface with monitor mode and standard I/O pins.

– Two I2S interfaces with DMA support, each with one input and one output.

Digital peripherals:

– External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,

and SDRAM devices.

– LCD controller with DMA support and a programmable display resolution of up to

1024H 768V. Supports monochrome and color STN panels and TFT color

panels; supports 1/2/4/8 bpp CLUT and 16/24-bit direct pixel mapping.

– SD/MMC card interface.

– Eight-channel General-Purpose DMA (GPDMA) controller can access all

memories on the AHB and all DMA-capable AHB slaves.

– Up to 164 General-Purpose Input/Output (GPIO) pins with configurable

pull-up/pull-down resistors and open-drain modes.

– GPIO registers are located on the AHB for fast access. GPIO ports have DMA

support.

– State Configurable Timer (SCT) subsystem on AHB.

– Four general-purpose timer/counters with capture and match capabilities.

– One motor control PWM for three-phase motor control.

– One Quadrature Encoder Interface (QEI).

– Repetitive Interrupt timer (RI timer).

– Windowed watchdog timer.

– Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes

of battery powered backup registers.

– Event recorder with 3 inputs to record event identification and event time; can be

battery powered. The event recorder is available on parts with on-chip flash only.

– Alarm timer; can be battery powered.

Digital peripherals available on flash-based parts LPC18xx only:

– Event monitor in the RTC power domain.

Analog peripherals:

– One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.

– Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.

Security (LPC18Sxx parts only):

– Hardware-based AES security engine programmable through an on-chip API.

– Two 128 bit secure OTP memories for AES key storage and customer use.

– Random number generator (RNG) accessible through AES API.

Unique ID for each device.

Power:

– Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator

for the core supply and the RTC power domain.

– RTC power domain can be powered separately by a 3 V battery supply.

– Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep

power-down.

– Processor wake-up from Sleep mode via wake-up interrupts from various

peripherals.

– Wake-up from Deep-sleep, Power-down, and Deep power-down modes via

external interrupts and interrupts generated by battery powered blocks in the RTC

power domain.

– Brownout detect with four separate thresholds for interrupt and forced reset.

– Power-On Reset (POR).

Available as 144-pin and 208-pin LQFP packages and as 100-pin, 180-pin, and

256-pin LBGA packages.